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ds05-20891-4e fujitsu semiconductor data sheet flash memory cmos 16 m (2 m 8/1 m 16) bit dual operation mbm29ds163te/be 10 n n n n description the mbm29ds163te/be is 16 m-bit, 1.8 v-only flash memory organized as 2 m bytes of 8 bits each or 1 m words of 16 bits each. the device is offered in 48-pin tsop (1) and 48-ball fbga packages. this device is designed to be programmed in system with standard system 1.8 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. (continued) n n n n product line up n n n n packages part no. mbm29ds163te/be10 power supply voltage (v) v cc = 2.0 v max address access time (ns) 100 max ce access time (ns) 100 max oe access time (ns) 35 + 0.2 v - 0.2 v 48-pin plastic tsop (1) 48-pin plastic tsop (1) 48-ball plastic fbga (fpt-48p-m19) (fpt-48p-m20) (bga-48p-m11) marking side marking side
mbm29ds163te/be 10 2 (continued) the device is organized into two banks, bank 1 and bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. this device is the same as fujitsus standard 1.8 v only flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. the standard device offers access time 100 ns, allowing operation of high-speed microprocessors without wait state. to eliminate bus contention the device has separate chip enable (ce ) , write enable (we ) , and output enable (oe ) controls. the device is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this invokes the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second (if already completely preprogrammed) . the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 1.8 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle is completed, the device internally resets to the read mode. the device also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. these locations need re-writing after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the device memory electrically erases the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
mbm29ds163te/be 10 3 n n n n features ? 0.23 m m m m m process technology ? simultaneous read/write operations (dual bank) host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations read-while-erase read-while-program ? single 1.8 v read, program, and erase minimized system level power requirements ? compatible with jedec-standard commands use the same software commands as e 2 proms ? compatible with jedec-standard worldwide pinouts 48-pin tsop (1) (package suffix : tn - normal bend type, tr - reversed bend type) 48-ball fbga (package suffix : pbt) ? minimum 100,000 program/erase cycles ? high performance 100 ns maximum access time ? sector erase architecture eight 4 k word and thirty-one 32 k word sectors in word mode eight 8 k byte and thirty-one 64 k byte sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? hiddenrom region 64 k byte of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of boot sectors, regardless of sector protection/unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ? data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? program suspend/resume ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector group protection hardware method disables any combination of sector groups from program or erase operations ? sector group protection set function by extended sector group protection command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin. ? in accordance with cfi (c ommon f lash memory i nterface) *: embedded erase tm and embedded program tm are trademarks of advanced micro devices , inc.
mbm29ds163te/be 10 4 n n n n pin assignments (continued) tsop (1) (fpt-48p-m19) (fpt-48p-m20) a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 n.c. we reset n.c. wp/acc ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 (marking side) mbm29ds163te/be normal bend a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by wp/acc n.c. reset we n.c. a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 (marking side) mbm29ds163te/be reverse bend
mbm29ds163te/be 10 5 (continued) fbga (top view) marking side (bga-48p-m11) a6 a 13 a5 a 9 a4 we a3 ry/by a2 a 7 a1 a 3 b6 a 12 b5 a 8 b4 reset b3 wp/ acc b2 a 17 b1 a 4 c6 a 14 c5 a 10 c4 n.c. c3 a 18 c2 a 6 c1 a 2 d6 a 15 d5 a 11 d4 a 19 d3 n.c. d2 a 5 d1 a 1 e6 a 16 e5 dq 7 e4 dq 5 e3 dq 2 e2 dq 0 e1 a 0 f6 byte f5 dq 14 f4 dq 12 f3 dq 10 f2 dq 8 f1 ce g6 dq 15 / a -1 g5 dq 13 g4 v cc g3 dq 11 g2 dq 9 g1 oe h6 v ss h5 dq 6 h4 dq 4 h3 dq 3 h2 dq 1 h1 v ss
mbm29ds163te/be 10 6 n n n n pin description pin function a 19 to a 0 , a -1 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector group unprotection byte selects 8-bit or 16-bit mode wp /acc hardware write protection/program acceleration n.c. no internal connection v ss device ground v cc device power supply
mbm29ds163te/be 10 7 n n n n block diagram n n n n logic symbol v ss v cc we a 19 to a 0 (a -1 ) cell matrix (bank 2) x-decoder y-gating & data latch cell matrix (bank 1) x-decoder y-gating & data latch dq 15 to dq 0 dq 15 to dq 0 byte wp/acc reset ry/by ce oe status control state control & command register bank 2 address bank 1 address 20 a 19 to a 0 we ry/by oe ce dq 15 to dq 0 16 or 8 reset a -1 byte wp/acc
mbm29ds163te/be 10 8 n n n n device bus operation mbm29ds163te/be user bus operations (byte = = = = v ih ) table mbm29ds163te/be user bus operations (byte = = = = v il ) table legend : l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see mbm29ds163te/be command definitions table. *2 : refer to the section on sector group protection. *3 : we can be v il if oe is v il , oe at v ih initiates the write operations. *4 : v cc must be between the minimum and maximum of the operation range. *5 : also used for the extended sector group protection. operation ce oe we a 0 a 1 a 6 a 9 dq 15 to dq 0 reset wp / acc auto-select manufacturer code* 1 llhlllv id code h x auto-select device code* 1 llhhllv id code h x read* 3 llha 0 a 1 a 6 a 9 d out hx standby h xxxxxx high-z h x output disable l h h x x x x high-z h x write (program/erase) l h l a 0 a 1 a 6 a 9 d in hx enable sector group protection* 2, * 4 lv id lhlv id xhx verify sector group protection* 2, * 4 llhlhlv id code h x temporary sector group unprotection* 5 xxxxxxx x v id x reset (hardware) /standby xxxxxxx high-z l x boot block sector write protection xxxxxxx x x l operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 7 to dq 0 reset wp / acc auto-select manufacturer code* 1 llh l lllv id code h x auto-select device code* 1 llh l hllv id code h x read* 3 llha -1 a 0 a 1 a 6 a 9 d out hx standby h x x x x x x x high-z h x output disable l h h x x x x x high-z h x write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in hx enable sector group protection * 2, * 4 lv id llhlv id xhx verify sector group protection* 2, * 4 llh l lhlv id code h x temporary sector group unprotection* 5 xxx x xxxx x v id x reset (hardware) /standby x x x x x x x x high-z l x boot block sector write protection x x x x x x x x x x l
mbm29ds163te/be 10 9 mbm29ds163te/be command definitions table (continued) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset* 1 word 1 xxxh f0h ?????????? byte read/reset* 1 word 3 555h aah 2aah 55h 555h f0h ra* 7 rd* 7 ???? byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h ia* 7 id* 7 ???? byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah program suspend 1 ba b0h ?????????? program resume 1 ba 30h ?????????? chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 ba b0h ?????????? erase resume 1 ba 30h ?????????? set to fast mode word 3 555h aah 2aah 55h 555h 20h ?????? byte aaah 555h aaah fast program* 2 word 2 xxxh a0h pa pd ???????? byte xxxh reset from fast mode* 2 word 2 ba 90h xxxh * 6 f0h ???????? byte ba xxxh extended sector group protection* 3 word 3 xxxh 60h spa 60h spa 40h spa* 7 sd* 7 ???? byte query* 4 word 1 55h 98h ?????????? byte aah hiddenrom entry word 3 555h aah 2aah 55h 555h 88h ?????? byte aaah 555h aaah hiddenrom program* 5 word 4 555h aah 2aah 55h 555h a0h (hra) pa pd ???? byte aaah 555h aaah
mbm29ds163te/be 10 10 (continued) *1 : both of these reset commands one equivalent. *2 : this command is valid while fast mode. *3 : this command is valid while reset = v id . *4 : the valid addresses are a 6 to a 0 . *5 : this command is valid while hiddenrom mode. *6 : the data "00h" is also acceptable. *7 : the fourth bus cycle is only for read. command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data hiddenrom erase* 5 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h byte aaah 555h aaah aaah 555h hiddenrom exit* 5 word 4 555h aah 2aah 55h ( hrba ) 555h 90h xxxh 00h ???? byte aaah 555h ( hrba ) aaah notes : address bits a 19 to a 11 = x = h or l for all address commands except or program address (pa) , sector address (sa) , and bank address (ba) . bus operations are defined in mbm29ds163te/be user bus operation (byte = v ih ) table and mbm29ds163te/be user bus operation (byte = v il ) table. ra = address of the memory location to be read ia = autoselect read address sets both the bank address specified at (a 19 , a 18 , a 17 , a 16 , a 15 ) and all the other a 6 , a 1 , a 0 , (a - 1 ) . pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 19 to a 15 ) rd = data read from location ra during read operation. id = device code/manufacture code for the address located by ia. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0) . sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hiddenrom area 29ds163te (top boot type) word mode : 0f8000h to 0fffffh byte mode : 1f0000h to 1fffffh 29ds163be (bottom boot type) word mode : 000000h to 007fffh byte mode : 000000h to 00ffffh hrba = bank address of the hiddenrom area 29ds163te (top boot type) : a 19 = a 18 = a 17 = a 16 = a 15 = v ih 29ds163be (bottom boot type) : a 19 = a 18 = a 17 = a 16 = a 15 = v il the system should generate the following address patterns : word mode : 555h or 2aah to addresses a 10 to a 0 byte mode : aaah or 555h to addresses a 10 to a 0 , and a- 1
mbm29ds163te/be 10 11 both read/reset commands are functionally equivalent, resetting the device to the read mode. command combinations not described in mbm29ds163te/be command definitions table are il- legal.
mbm29ds163te/be 10 12 mbm29ds163te/be sector group protection verify autoselect codes table *1 : a -1 is for byte mode. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : ba is bank address which is needed only in command autoselect mode. expanded autoselect code table (b) : byte mode (w) : word mode hz : high-z type a 19 to a 12 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code ba *3 v il v il v il v il 04h device code mbm29ds163te byte ba *3 v il v il v ih v il 95h word x 2295h MBM29DS163BE byte ba *3 v il v il v ih v il 96h word x 2296h extend code mbm29ds163te/be byte ba *3 v il v ih v ih v il 05h word x 2205h sector group protection sector group addresses v il v ih v il v il 01h *2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 00000 0000000100 device code mbm29ds 163te (b) 95h a -1 hzhzhzhzhzhzhz10010101 (w) 2295h 0 01000 1010010101 mbm29ds 163be (b) 96h a -1 hzhzhzhzhzhzhz10010110 (w) 2296h 0 01000 1010010110 extend code mbm29ds 163te/be (b) 05h a -1 hzhzhzhzhzhzhz00000101 (w) 2205h 0 01000 1000000101 sector group protection 01h a -1 /0 00000 0000000001
mbm29ds163te/be 10 13 n n n n flexible sector-erase architecture sector address table (mbm29ds163te) (continued) bank sec- tor sector address sector size ( kbytes / kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0 0 0 0 0 x x x 64/32 000000h to 00ffffh 000000h to 007fffh sa1 0 0 0 0 1 x x x 64/32 010000h to 01ffffh 008000h to 00ffffh sa2 0 0 0 1 0 x x x 64/32 020000h to 02ffffh 010000h to 017fffh sa3 0 0 0 1 1 x x x 64/32 030000h to 03ffffh 018000h to 01ffffh sa4 0 0 1 0 0 x x x 64/32 040000h to 04ffffh 020000h to 027fffh sa5 0 0 1 0 1 x x x 64/32 050000h to 05ffffh 028000h to 02ffffh sa6 0 0 1 1 0 x x x 64/32 060000h to 06ffffh 030000h to 037fffh sa7 0 0 1 1 1 x x x 64/32 070000h to 07ffffh 038000h to 03ffffh sa8 0 1 0 0 0 x x x 64/32 080000h to 08ffffh 040000h to 048000h sa9 0 1 0 0 1 x x x 64/32 090000h to 09ffffh 048000h to 04ffffh sa10 0 1 0 1 0 x x x 64/32 0a0000h to 0affffh 050000h to 058000h sa11 0 1 0 1 1 x x x 64/32 0b0000h to 0bffffh 058000h to 05ffffh sa12 0 1 1 0 0 x x x 64/32 0c0000h to 0cffffh 060000h to 068000h sa13 0 1 1 0 1 x x x 64/32 0d0000h to 0dffffh 068000h to 06ffffh sa14 0 1 1 1 0 x x x 64/32 0e0000h to 0effffh 070000h to 078fffh sa15 0 1 1 1 1 x x x 64/32 0f0000h to 0fffffh 078000h to 07ffffh sa16 1 0 0 0 0 x x x 64/32 100000h to 10ffffh 080000h to 088000h sa17 1 0 0 0 1 x x x 64/32 110000h to 11ffffh 088000h to 08ffffh sa18 1 0 0 1 0 x x x 64/32 120000h to 12ffffh 090000h to 098000h sa19 1 0 0 1 1 x x x 64/32 130000h to 13ffffh 098000h to 09ffffh sa20 1 0 1 0 0 x x x 64/32 140000h to 14ffffh 0a0000h to 0a7fffh sa21 1 0 1 0 1 x x x 64/32 150000h to 15ffffh 0a8000h to 00afffh sa22 1 0 1 1 0 x x x 64/32 160000h to 16ffffh 0b0000h to 0b7000h sa23 1 0 1 1 1 x x x 64/32 170000h to 17ffffh 0b8000h to 0bffffh
mbm29ds163te/be 10 14 (continued) notes : the address range is a 19 : a -1 if in byte mode (byte = v il ) . the address range is a 19 : a 0 if in word mode (byte = v ih ) . bank sec- tor sector address sector size ( kbytes / kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa2411000xxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa2511001xxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa2611010xxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa2711011xxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa2811100xxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh sa2911101xxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa3011110xxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7000h sa3111111000 8/4 1f 0000h to 1f1fffh 0f8000h to 0f8fffh sa3211111001 8/4 1f 2000h to 1f3fffh 0f9000h to 0f9fffh sa3311111010 8/4 1f 4000h to 1f5fffh 0fa000h to 0fafffh sa3411111011 8/4 1f 6000h to 1f7fffh 0fb000h to 0fbfffh sa3511111100 8/4 1f 8000h to 1f9fffh 0fc000h to 0fcfffh sa3611111101 8/4 1fa000h to 1fbfffh0fd000h to 0fdfffh sa3711111110 8/4 1fc000h to 1fdfffh0fe000h to 0fefffh sa3811111111 8/4 1fe000h to 1fffffh0ff000h to 0fffffh
mbm29ds163te/be 10 15 sector address table (MBM29DS163BE) (continued) bank sec- tor sector address sector size ( kbytes / kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa38 1 1 1 1 1 x x x 64/32 1f0000h to 1fffffh 0f8000h to 0fffffh sa37 1 1 1 1 0 x x x 64/32 1e0000h to 1effffh 0f0000h to 0f7fffh sa36 1 1 1 0 1 x x x 64/32 1d0000h to 1dffffh 0e8000h to 0effffh sa35 1 1 1 0 0 x x x 64/32 1c0000h to 1cffffh 0e0000h to 0e7fffh sa34 1 1 0 1 1 x x x 64/32 1b0000h to 1bffffh 0d8000h to 0dffffh sa33 1 1 0 1 0 x x x 64/32 1a0000h to 1affffh 0d0000h to 0d7fffh sa32 1 1 0 0 1 x x x 64/32 190000h to 19ffffh 0c8000h to 0cffffh sa31 1 1 0 0 0 x x x 64/32 180000h to 18ffffh 0c0000h to 0c7fffh sa30 1 0 1 1 1 x x x 64/32 170000h to 17ffffh 0b8000h to 0bffffh sa29 1 0 1 1 0 x x x 64/32 160000h to 16ffffh 0b0000h to 0b7fffh sa28 1 0 1 0 1 x x x 64/32 150000h to 15ffffh 0a8000h to 0affffh sa27 1 0 1 0 0 x x x 64/32 140000h to 14ffffh 0a0000h to 0a7fffh sa26 1 0 0 1 1 x x x 64/32 130000h to 13ffffh 098000h to 09ffffh sa25 1 0 0 1 0 x x x 64/32 120000h to 12ffffh 090000h to 097fffh sa24 1 0 0 0 x x x x 64/32 110000h to 11ffffh 088000h to 08ffffh sa23 1 0 0 0 0 x x x 64/32 100000h to 10ffffh 080000h to 087fffh sa22 0 1 1 1 1 x x x 64/32 0f0000h to 0fffffh 078000h to 07ffffh sa21 0 1 1 1 0 x x x 64/32 0e0000h to 0effffh 070000h to 077fffh sa20 0 1 1 0 1 x x x 64/32 0d0000h to 0dffffh 068000h to 06ffffh sa19 0 1 1 0 0 x x x 64/32 0c0000h to 0cffffh 060000h to 067fffh sa18 0 1 0 1 1 x x x 64/32 0b0000h to 0bffffh 058000h to 05ffffh sa17 0 1 0 1 0 x x x 64/32 0a0000h to 0affffh 050000h to 057fffh sa16 0 1 0 0 1 x x x 64/32 090000h to 0fffffh 048000h to 04ffffh sa15 0 1 0 0 0 x x x 64/32 080000h to 08ffffh 040000h to 047fffh
mbm29ds163te/be 10 16 (continued) notes : the address range is a 19 : a -1 if in byte mode (byte = v il ) . the address range is a 19 : a 0 if in word mode (byte = v ih ) . bank sec- tor sector address sector size ( kbytes / kwords ) ( 8) address range ( 16) address range bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa1400111xxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa1300110xxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa1200101xxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa1100100xxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa1000011xxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa9 00010xxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa8 00001xxx 64/32 010 000h to 01ffffh 008000h to 008fffh sa7 00000111 8/4 00e000h to 00ffffh 007000h to 007fffh sa6 00000110 8/4 00c000h to 00dfffh 006000h to 006fffh sa5 00000101 8/4 00a000h to 00bfffh 005000h to 005fffh sa4 00000100 8/4 00 8000h to 009fffh 004000h to 004fffh sa3 00000011 8/4 00 6000h to 007fffh 003000h to 003fffh sa2 00000010 8/4 00 4000h to 005fffh 002000h to 002fffh sa1 00000001 8/4 00 2000h to 003fffh 001000h to 001fffh sa0 00000000 8/4 00 0000h to 001fffh 000000h to 000fffh
mbm29ds163te/be 10 17 sector group addresses (mbm29ds163te) table (top boot block) sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000xxx sa0 sga1 00001xxx sa1 to sa3 00010xxx 00011xxx sga2 0 0 1xxxxxsa4 to sa7 sga3 0 1 0 x x x x x sa8 to sa11 sga4 0 1 1 x x x x x sa12 to sa15 sga5 1 0 0 x x x x x sa16 to sa19 sga6 1 0 1 x x x x x sa20 to sa23 sga7 1 1 0 x x x x x sa24 to sa27 sga8 11100xxx sa28 to sa30 11101xxx 11110xxx sga9 11111000 sa31 sga1011111001 sa32 sga1111111010 sa33 sga1211111011 sa34 sga1311111100 sa35 sga1411111101 sa36 sga1511111110 sa37 sga1611111111 sa38
mbm29ds163te/be 10 18 sector group addresses (MBM29DS163BE) table (bottom boot block) sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000000 sa0 sga1 00000001 sa1 sga2 00000010 sa2 sga3 00000011 sa3 sga4 00000100 sa4 sga5 00000101 sa5 sga6 00000110 sa6 sga7 00000111 sa7 sga8 00001xxx sa8 to sa10 00010xxx 00011xxx sga9 0 0 1 x x x x x sa11 to sa14 sga10 0 1 0 x x x x x sa15 to sa18 sga11 0 1 1 x x x x x sa19 to sa22 sga12 1 0 0 x x x x x sa23 to sa26 sga13 1 0 1 x x x x x sa27 to sa30 sga14 1 1 0 x x x x x sa31 to sa34 sga15 11100xxx sa35 to sa37 11101xxx 11110xxx sga16 1 1 1 1 1 x x x sa38
mbm29ds163te/be 10 19 common flash memory interface code table (continued) description a 6 to a 0 dq 15 to dq 0 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 2h : amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min (write/erase) dq 7 to dq 4 : v, dq 3 to dq 0 : 100 mv 1bh 0018h v cc max (write/erase) dq 7 to dq 4 : v, dq 3 to dq 0 : 100 mv 1ch 0022h v pp min voltage 1dh 0000h v pp max voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min size buffer write 2 n m s 20h 0000h typical timeout per individual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max timeout for byte/word write 2 n times typical 23h 0005h max timeout for buffer write 2 n times typical 24h 0000h max timeout per individual block erase 2 n times typical 25h 0004h max timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0015h flash device interface description 28h 29h 0002h 0000h max number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0002h erase block region 1 information 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 001eh 0000h 0000h 0001h
mbm29ds163te/be 10 20 (continued) description a 6 to a 0 dq 15 to dq 0 query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0032h address sensitive unlock 0h = required 1h = not required 45h 0000h erase suspend 0h = not supported 1h = to read only 2h = to read & write 46h 0002h sector protection 0h = not supported x = number of sectors in per group 47h 0001h sector temporary unprotection 00h = not supported 01h = supported 48h 0001h sector protection algorithm 49h 0004h number of sector for bank 2 00h = not supported 4ah 0018h burst mode type 00h = not supported 4bh 0000h page mode type 00h = not supported 4ch 0000h acc (acceleration) supply minimum 00h = not supported, dq 7 to dq 4 : v, dq 3 to dq 0 : 100 mv 4dh 0085h acc (acceleration) supply maximum 00h = not supported, dq 7 to dq 4 : v, dq 3 to dq 0 : 100 mv 4eh 0095h boot type 02h = MBM29DS163BE 03h = mbm29ds163te 4fh 00xxh program suspend 00h = not supported 01h = supported 50h 0001h
mbm29ds163te/be 10 21 n n n n functional description simultaneous operation the device has a feature, that is capable of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation) , in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . the bank selection can be selected by bank address (a 19 to a 15 ) with zero latency. the device has two banks which contain bank 1 (8 kb eight sectors, 64 kb seven sectors) and bank 2 (64 kb twenty-four sectors) . the simultaneous operation cannot execute multi-function mode in the same bank. simultaneous operation table shows the combinations for simultaneous operation (refer to bank-to-bank read/write timing diagram in n timing diagram) . simultaneous operation table * : erase operation may also be supended to read from or program to a sector not being erased. read mode the device has two control functions to be satisfied to obtaining data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time) . when reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h or l. the reset pin must be held low during v cc rampup to insure that device powers up correctly. (refer to power on/off timing diagram in n timing diagram.) standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l) . under this condition the current consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh as wake up time for outputs to be valid for read access. in the standby mode the outputs are in the high impedance state, independently of the oe input. case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mbm29ds163te/be 10 22 automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of the device data. this mode can be useful in the application such as a handy terminal which requires low power consumption. to activate this mode, the device automatically switches themselves to low power mode when the device ad- dresses remain stable during access time of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level) . during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically, and the device reads the data for changed addresses. output disable with the oe input at a logic high level (v ih ) , output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (10.0 v to 11.0 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 (a -1 ) . (see mbm29ds163te/be user bus operations (byte = v ih ) table and mbm29ds163te/be user bus operations (byte = v il ) table in n device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29ds163te/be command definitions table in n device bus operation. word 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and word 1 (a 0 = v ih ) represents the device identifier code. these two bytes/words are given in mbm29ds163te/be sector group protection verify au- toselect codes table and expanded autoselect code table in n device bus operation. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see mbm29ds163te/be sector group protection verify autoselect codes table and expanded autoselect code table in n device bus operation.) in case of applying v id on a 9 , since both bank 1 and bank 2 enters autoselect mode, the simultenous operation can not be executed. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector group protection the device features hardware sector group protection. this feature will disable both program and erase opera- tions in any combination of twenty five sector groups of memory. (see sector group addresses (mbm29ds163te) table and sector group addresses (MBM29DS163BE) table in n flexible sector-
mbm29ds163te/be 10 23 erase architecture.) the sector group protection feature is enabled using programming equipment at the users site. the device is shipped with all sector groups unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v) , ce = v il and a 6 = a 0 = v il , a 1 = v ih . the sector group addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. sector address (mbm29ds163te) table and sector address (MBM29DS163BE) table in n flexible sector-erase architecture define the sector address for each of the seventy one (71) individual sectors, and tsector group addresses (mbm29ds163te) table and sector group addresses (MBM29DS163BE) table in n flexible sector-erase architec- ture define the sector group address for each of the twenty five (25) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see sector group protection timing diagram in n timing diagram and sector group protection algorithm in n flow chart for sector group protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector group. see mbm29ds163te/be sector group protection verify autoselect codes table and expanded au- toselect code table in n device bus operation for autoselect codes. temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the device in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ) . during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad- dresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to temporary sector group unprotection timing diagram in n timing diagram and temporary sector group unprotection algorithm in n flow chart. extended sector group protection in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables to protect sector group by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector group addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector group to be protected (recommend to set v il for the other addresses pins) , and write extended sector group protection command (60h) . a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h) . following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output is logical 0, please repeat to write extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . (refer to extended sector group protection timing diagram in n timing diagram and extended sector group protection algorithm in n flow chart.)
mbm29ds163te/be 10 24 reset hardware reset the device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional t rh before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see reset , ry/by timing diagram in n timing diagram for the timing diagram. refer to temporary sector group unprotection for additional functionality. boot block sector protection the write protection function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the two outermost 8 k byte boot sectors independently of whether those sectors are protected or unprotected using the method described in sector protection/unprotection. the two outermost 8 k byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (mbm29ds163te : sa37 and sa38, MBM29DS163BE : sa0 and sa1) if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 8 k byte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in sector protection/unprotection. accelerated program operation the device offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60 % . this function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see accelerated program timing diagram in n timing diagram.
mbm29ds163te/be 10 25 n n n n command definitions the device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. some commands require bank address (ba) input. when command sequences are inputed to bank being read, the commands have priority over reading. mbm29ds163te/be command definitions table in n device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. micro- processor read cycles retrieve array data from the memory. the device remain enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read character- istics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by firstly writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and actual data of memory cell can be read from the another bank. following the command write, a read cycle from address (ba) 00h retrieves the manufacture code of 04h. a read cycle from address (ba) 01h for 16 ( (ba) 02h for 8) returns the device code. (see mbm29ds163te/ be sector group protection verify autoselect codes table and expanded autoselect code table in n device bus operation.) the sector state (protection or unprotection) will be informed by address (ba) 02h for 16 ( (ba) 04h for 8) . scanning the sector group addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verify sector group protection on the protected sector. (see mbm29ds163te/be user bus operations (byte = v ih ) table and mbm29ds163te/be user bus operations (byte = v il ) table in n device bus operation.) the manufacture and device codes can be allowed reading from selected bank. to read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the flash memory, the device and manu- facture codes should be read from the other bank which doesnt contain the software. to terminate the operation, it is necessary to write the read/reset command sequence into the register. to execute the autoselect command during the operation, writing read/reset command sequence must precede the autoselect command.
mbm29ds163te/be 10 26 byte/word programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device automatically provides adequate internally generated program pulses and verify programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling) , dq 6 (toggle bit) , or ry/by . the data polling and toggle bit must be performed at the memory location being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which the device return to the read mode and addresses are no longer latched. (see hardware sequence flags , hardware sequence flags.) therefore the device requires that a valid address to the device be supplied by the system at this particular moment. hence data polling must be performed at the memory location being programmed. any commands written to the chip during this period are ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. embedded program tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. program suspend/resume the program suspend command allows the system to interrupt a program operation so that data can be read from any address. writing the program suspend command (b0h) during the embedded program operation immediately suspends the programming. the program suspend command may also be issued during a pro- gramming operation while an erase is suspended. the bank addresses of sector being programed should be set when writing the program suspend command. when the program suspend command is written during a programming process, the device halts the program operation within 1 m s and updates the status bits. after the program operation has been suspended, the system can read data from any address. the data at program-suspended address is not valid. normal read timing and command definitions apply. after the program resume command (30h) is written, the device reverts to programming. the bank addresses of sector being suspended should be set when writing the program resume command. the system can deter- mine the status of the program operation using the dq 7 or dq 6 status bits, just as in the standard program operation. see write operation status for more information. the system may also write the autoselect command sequence when the device in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the program resume command (address bits are bank address) to exit the program suspend mode and continue the programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device has resumed programming. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command.
mbm29ds163te/be 10 27 chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function) . the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) , or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which the device returns to read the mode. chip erase time : sector erase time all sectors + chip program time (preprogramming) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we which happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation begins. multiple sectors are erased concurrently by writing the six bus cycle operations on mbm29ds163te/be com- mand definitions in n user bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow otherwise that command will not be accepted and erasure does not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re- enabled after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we whichever happens first will initiate the execution of the sector erase command (s) . if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. resetting the device once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70) . sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (preprogram function) . when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) , or ry/by . the sector erase begins after the t tow time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time : [sector erase time + sector program time (preprogramming) ] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations.
mbm29ds163te/be 10 28 erase suspend/resume the erase suspend command allows the user to interrupt sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erased or erase-suspended should be set when writting the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device takes a maximum of t spd to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin is at high-z and the dq 7 bit is at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation is suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point is ignored. another erase suspend com- mand is written after the chip resumes erasing. extended command (1) fast mode the device has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to embedded program tm algorithm for fast mode in n flow chart.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd) . (refer to embedded program tm algorithm for fast mode in n flow chart.) (3) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. this allows device-independent, jedec id-independent, and forward-and backward-compatible software sup- port for the specified flash device families. refer to cfi specification in detail.
mbm29ds163te/be 10 29 the operation is initiated by writing the query command (98h) into the command register. the bank address should be set when writing this command. then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. following the command write, a read cycle from specific address retrives device information. please note that output data of upper byte (dq 15 to dq 8 ) is 0 in word mode (16 bit) read. refer to the cfi code table. to terminate operation, it is necessary to write the read/reset command sequence into the register. (see command flash memory interface code in n flexible sector-erase architecture.) hiddenrom region the hiddenrom feature provides flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hiddenrom region is protected, any further modification of that region is not allowed. this ensures the security of the esn once the product is shipped to the field. the hiddenrom region is 64 k bytes in length and is stored at the same address of the 8 kb 8 sectors. the mbm29ds163te occupies the address of the byte mode 1f0000h to 1fffffh (word mode 0f8000h to 0fffffh) and the MBM29DS163BE type occupies the address of the byte mode 000000h to 00ffffh (word mode 000000h to 007fffh) . after the system writes the enter hiddenrom command sequence, the system reads the hiddenrom region by using the addresses normally occupied by the boot sectors. that is, the device sends all commands that would normally be sent to the boot sectors to the hiddenrom region. this mode of operation continues until the system issues the exit hiddenrom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. hiddenrom entry command the device has hiddenrom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. program/erase is possible in this area until it becomes protected. however once it is protected, it is impossible to unprotect, use this command with caution. hiddenrom area is 64 k byte and in the same address area of 8 kb sector. the address of top boot is 1f0000h to 1fffffh at byte mode (0f8000h to 0fffffh at word mode) and the bottom boot is 000000h to 00ffffh at byte mode (000000h to 007fffh at word mode) . these areas are normally the boot block area (8kb 8 sector) . therefore, write the hiddenrom entry command sequence to enter the hiddenrom area. this is called hiddenrom mode as the hiddenrom area appears. sector other than the boot block area could be read during hiddenrom mode. read/program/earse of the hiddenrom area is allowed during hiddenrom mode. write the hiddenrom reset command sequence to exit the hiddenrom mode. the bank address of the hiddenrom should be set on the third cycle of this reset command sequence. hiddenrom program command to program data to hiddenrom area, write the hiddenrom program command sequence during hiddenrom mode. this command is the same as the program command in usual except to write the command during hiddenrom mode. therefore the detection of completion method is the same as described, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. need to pay attention to the address to be programmed. if the address other than the hiddenrom area is selected to program, data of the address will be changed. hiddenrom erase command to erase the hiddenrom area, write the hiddenrom erase command sequence during hiddenrom mode. this command is same as the sector erase command in the past except to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. need to pay attention to the sector address to be erased. if the sector address other than the hiddenrom area is selected, the data of the sector will be changed.
mbm29ds163te/be 10 30 hiddenrom protect command there are two methods to protect the hiddenrom area. one is to write the sector group protect setup command (60h) , set the sector address in the hiddenrom area and (a 6 , a 1 , a 0 ) = (0, 1, 0) , and write the sector group protect command (60h) during the hiddenrom mode. the same command sequence could be used because, it is just as the extension sector group protect in the past except that it is in the hiddenrom mode and it does not apply high voltage to reset pin. please refer to function explanation extentended sector group protection for details of extention sector group protect setting. the other method is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom area and (a 6 , a 1 , a 0 ) = (0, 1, 0) , and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 1 , a 0 ) = (0, 1, 0) and the sector address in the hiddenrom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 will appear on dq 0 if it is not protected. please apply write pulse again. the same command sequence could be used for the above method because other than the hiddenrom mode, it is the same with the sector group protect in the past. please refer to function explanation sector group protection for details of the sector group protect setting. other sector group will be effected if the address other than those for hiddenrom area is selected for the sector group address. once it is protected, protection cannot be cancelled; so pay the closest attention. write operation status detailed in hardware sequence flags table are all the status flags that determine the status of the bank for the current mode operation. the read operation from the bank which does not operate embedded algorithm returns data of memory cells. these bits offer a method for determining whether a embedded algorithm is properly completed. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consectively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non- erasing sector is consectively read. this allows users to determine which sectors are in erase and which are not. the status flag is not output from bank (non-busy bank) which does not execute embedded algorithm. for example, there is bank (busy bank) now executing embedded algorithm. when the read sequence is [1] < busy bank > , [2] < non-busy bank > , [3] < busy bank > , the dq 6 is toggling in the case of [1] and [3]. in case of [2], the data of memory cells are outputted. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in the [1] and [3]. in the erase suspend read mode, dq 2 is toggled in the [1] and [3]. in case of [2], the data of memory cell is outputted. hardware sequence flags table status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle* program suspended mode program suspend read (program suspended sector) data data data data data program suspend read (non-program suspended sector) data data data data data erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1* exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29ds163te/be 10 31 * : successive reads from the erasing or erase-suspend sector cause dq 2 to toggle. reading from non-erase suspend sector address indicates logic 1 at the dq 2 bit. notes : dq 0 and dq 1 are reserve pins for future use. dq 4 is fujitsu internal use only. dq 7 data polling the device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read device will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read device will produce a 1 on dq 7 . the flowchart for data polling (dq 7 ) is shown in data polling algorithm in n flow chart. for programming, the data polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address of sectors being erased, not protected sectors. otherwise, the status may be invalid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to completion, the device data pins (dq 7 ) may change asyn- chronously while the output enable (oe ) is asserted low. this means that device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if device has completed the embedded algorithm operation and dq 7 has a valid data, data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see hardware sequence flags table.) see data polling during embedded algorithm operation timing diagram in n timing diagram for the data polling timing specifications and diagrams. dq 6 toggle bit i the device also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will results in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during pro- gramming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written is protected, the toggle bit will toggle for about 1 m s and then stop toggling with data unchanged. in erase, device will erase all selected sectors except for ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 m s and then drop back into read mode, having data unchanged. either ce or oe toggling will cause dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erased or is erase-suspended. when a bank is actively erased (that is, the embedded erase algorithm is in progress) , dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during erase-suspend-program cause dq 6 to toggle.to operate toggle bit function properly, ce or oe must be high when bank address is changed.
mbm29ds163te/be 10 32 see toggle bit during embedded algorithm operation timing diagram in n timing diagram for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of device under this condition. the ce circuit will partially power down device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in mbm29ds163te/be user bus operations (byte = v ih ) table and mbm29ds163te/be user bus operations (byte = v il ) table at n device bus operation the dq 5 failure condition may also appear if a user tries to program a non blank location without pre-erase. in this case the device locks out and never complete the embedded algorithm operation. hence, the system never read valid data on dq 7 bit and dq 6 never stop toggling. once device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since device was incorrectly used. if this occurs, reset device with command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence sector erase time-out will begin. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0) , the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags table : hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also toggle bit status and dq2 vs. dq6 in n timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed. reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the
mbm29ds163te/be 10 33 first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to toggle bit algorithm in n flow chart.) table 11 toggle bit status * : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. ry/by ready/busy the device provides a ry/by open-drain output pin as a way to indicate to the host system that embedded algorithms are either in progress or has been completed. if output is low, device is busy with either a program or erase operation. if output is high, device is ready to accept any read/write or erase operation. when ry/by pin is low, device will not accept any additional program or erase commands. if the device is placed in an erase suspend mode, ry/by output will be high. during programming, ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, ry/by pin is driven low after the rising edge of the sixth write pulse. ry/by pin will indicate a busy condition during reset pulse. refer to ry/by timing diagram during program/erase operations and reset , ry/by timing diagram in n timing diagram for a detailed timing diagram. ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . byte/word configuration byte pin selects byte (8-bit) mode or word (16-bit) mode for the device. when this pin is driven high, device operates in word (16-bit) mode. data is read and programmed at dq 15 to dq 0 . when this pin is driven low, device operates in byte (8-bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit, and dq 14 to dq 8 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 15 to dq 8 and dq 7 to dq 0 bits are ignored. refer to word mode configuration timing, byte mode configuration timing diagram and byte timing diagram for write operations in n timing diagram for the timing diagram. data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up device automatically resets internal state mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle* erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1*
mbm29ds163te/be 10 34 machine in read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29ds163te/be 10 35 n n n n absolute maximum ratings *1 : minimum dc voltage on input or i/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. *2 : minimum dc input voltage on a 9 , oe and reset pins is - 0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc ) does not exceed + 9.0 v.maximum dc input voltage on a 9 , oe and reset pins is + 11.5 v which may positive overshoot to + 12.5 v for periods of up to 20 ns. *3 : minimum dc input voltage on wp /acc pin is - 0.5 v. during voltage transitions, wp /acc pin may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is + 10.5 v which may positive overshoot to + 12.0 v for periods of up to 20 ns when vcc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions note : operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1 v in , v out - 0.5 v cc + 0.5 v power supply voltage * 1 v cc - 0.5 + 3.0 v a 9 , oe , and reset * 2 v in - 0.5 + 11.5 v wp /acc * 3 v acc - 0.5 + 10.5 v parameter symbol ranges unit min max ambient temperature t a - 40 + 85 c power supply voltage v cc + 1.8 + 2.2 v
mbm29ds163te/be 10 36 n n n n maximum overshoot/maximum undershoot 0.2 v cc - 0.5 v 20 ns - 2.0 v 20 ns 20 ns maximum undershoot waveform v cc + 0.5 v 0.8 v cc v cc + 2.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 1 + 11.0 v v cc + 0.5 v + 12.0 v 20 ns 20 ns 20 ns note : this waveform is applied for a 9 , oe, and reset. maximum overshoot waveform 2
mbm29ds163te/be 10 37 n n n n dc characteristics *1 : i cc current listed includes both the dc operating current and the frequency dependent component. *2 : ii cc active while embedded algorithm (program or erase) is in progress. *3 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : applicable for only v cc applying. *5 : embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol test conditions min max unit input leakage current i li v in = v ss to v cc , v cc = v cc max - 1.0 + 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max - 1.0 + 1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max a 9 , oe , reset = 11.0 v ? 35 m a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 5 mhz byte ? 16 ma word 16 ce = v il , oe = v ih , f = 1 mhz byte ? 4 ma word 4 v cc active current * 2 i cc2 ce = v il , oe = v ih ? 25 ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v ? 5 m a v cc current (standby, reset) i cc4 v cc = v cc max, we /acc = v cc 0.3 v, reset = v ss 0.3 v ? 5 m a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v ? 5 m a v cc active current * 5 (read-while-program) i cc6 ce = v il , oe = v ih byte ? 25 ma word ? 25 v cc active current * 5 (read-while-erase) i cc7 ce = v il , oe = v ih byte ? 25 ma word ? 25 v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih ? 15 ma wp /acc accelerated program current i acc v cc = v cc max wp /acc = v acc max ? 10 ma input low level v il ?- 0.5 0.2 v cc v input high level v ih ? 0.8 v cc v cc + 0.3 v voltage for wp /acc sector protection/unprotection and program acceleration * 4 v acc ? 8.5 9.5 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id ? 10.0 11.0 v output low voltage level v ol i ol = 100 m a, v cc = v cc min ? 0.1 v output high voltage level v oh i oh = - 100 m av cc - 0.1 ? v
mbm29ds163te/be 10 38 n n n n ac characteristics ? read only operations characteristics * : test conditions : output load : c l = 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or 2.0 v timing measurement reference level input : 0.5 v cc f output : 0.5 v cc f parameter symbol condition value * unit jedec standard min max read cycle time t avav t rc ? 100 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 100 ns chip enable to output delay t elqv t ce oe = v il ? 100 ns output enable to output delay t glqv t oe ?? 35 ns chip enable to output high-z t ehqz t df ?? 30 ns output enable to output high-z t ghqz t df ?? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ? 0 ? ns reset pin low to read mode ? t ready ?? 20 m s ce or byte switching low or high ? t elfl t elfh ?? 5ns c l device under test note : c l = 30 pf including jig capacitance
mbm29ds163te/be 10 39 ? write/erase/program operations (continued) parameter symbol value * 1 unit jedec standard min typ max write cycle time t avav t wc 100 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low during toggle bit polling ? t aso 15 ?? ns address hold time t wlax t ah 50 ?? ns address hold time from ce or oe high during toggle bit polling ? t aht 0 ?? ns data setup time t dvwh t ds 50 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read ? t oeh 0 ?? ns toggle and data polling 10 ?? ns ce high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? ns read recover time before write t ghel t ghel 0 ?? ns ce setup time t elwl t cs 0 ?? ns we setup time t wlel t ws 0 ?? ns ce hold time t wheh t ch 0 ?? ns we hold time t ehwh t wh 0 ?? ns write pulse width t wlwh t wp 50 ?? ns ce pulse width t eleh t cp 50 ?? ns write pulse width high t whwl t wph 35 ?? ns ce pulse width high t ehel t cph 35 ?? ns programming operation byte t whwh1 t whwh1 ? 8 ?m s word ? 16 ?m s sector erase operation* 1 t whwh2 t whwh2 ? 1 ? s v cc setup time ? t vcs 50 ??m s rise time to v id * 2 ? t vidr 500 ?? ns rise time to v acc * 3 ? t vaccr 500 ?? ns voltage transition time* 2 ? t vlht 4 ??m s write pulse width* 2 ? t wpp 100 ??m s oe setup time to we active* 2 ? t oesp 4 ??m s ce setup time to we active* 2 ? t csp 4 ??m s recover time from ry/by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns
mbm29ds163te/be 10 40 (continued) *1 : does not include the preprogramming time. *2 : for sector group protection operation. *3 : for accelerated program operation. parameter symbol value * 1 unit jedec standard min typ max reset high level period before read ? t rh 200 ?? ns byte switching low to output high-z ? t flqz ?? 30 ns byte switching high to output active ? t fhqv ?? 90 ns program/erase valid to ry/by delay ? t busy ?? 90 ns delay time from embedded output enable ? t eoe ?? 90 ns erase time-out time ? t tow 50 ??m s erase suspend transition time ? t spd ?? 20 m s power on / off time ? t ps ?? 100 ns
mbm29ds163te/be 10 41 n n n n erase and programming performance n n n n tsop (1) pin capacitance notes : test conditions t a = + 25 c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. n n n n fbga pin capacitance notes : test conditions t a = + 25 c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. parameter limit unit comments min typ max sector erase time ? 110s excludes programming time prior to erasure word programming time ? 16 360 m s excludes system-level overhead byte programming time ? 8 300 m s chip programming time ?? 50 s excludes system-level overhead program/erase cycle 100,000 ?? cycle ? parameter symbol test setup typ max unit input capacitance c in v in = 06.07.5pf output capacitance c out v out = 0 8.5 12.0 pf control pin capacitance c in2 v in = 0 8.0 11.0 pf wp /acc pin capacitance c in3 v in = 0 21.5 22.5 pf parameter symbol test setup typ max unit input capacitance c in v in = 06.07.5pf output capacitance c out v out = 0 8.5 12.0 pf control pin capacitance c in2 v in = 0 8.0 10.0 pf wp /acc pin capacitance c in3 v in = 0 17.0 18.0 pf
mbm29ds163te/be 10 42 n n n n timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l" any change permitted does not apply will be steady will change from h to l will change from l to h changing state unknown center line is high- impedance "off" state address address stable high-z high-z ce oe we outputs output valid data t rc t acc t oe t df t ce t oh t oeh read operation timing diagram
mbm29ds163te/be 10 43 address ce reset outputs high-z output valid address stable t rc t acc t rh t rp t rh t ce t oh hardware reset/read operation timing diagram reset v cc address data 0 v t ps v cc 1.8 v t ps 1.8 v valid data in valid data out t rh t acc power on/off timing diagram
mbm29ds163te/be 10 44 address data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t oh t oe t cs t ch t df alternate we controlled program operation timing diagram notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode) .
mbm29ds163te/be 10 45 address data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh alternate ce controlled program operation timing diagram notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode) .
mbm29ds163te/be 10 46 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa * t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h 30h for sector erase chip/sector erase operation timing diagram * : sa is the sector address for sector erase. addresses = 555h (word) , aaah (byte) for chip erase. note: these waveforms are for the 16 mode (the addresses differ from 8 mode) .
mbm29ds163te/be 10 47 t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data * data polling during embedded algorithm operation timing diagram * : dq 7 = valid data (the device has completed the embedded operation) .
mbm29ds163te/be 10 48 t aht ce address we ry/by oe dq 6 /dq 2 t dh t aso t oeph t aht t as t ceph t oe t ce t busy t oeh t oeh data toggle data toggle data toggle data stop toggling output valid * toggle bit i during embedded algorithm operation timing diagram * : dq 6 stops toggling (the device has completed the embedded operation) .
mbm29ds163te/be 10 49 ce oe address dq t ghwl t df t oe we t wp t oeh t as ba1 read command command read read read ba2 (555h) ba2 (pa) ba2 (pa) ba1 ba1 t ce t dh t df t ds (a0h) (pd) t acc t aht t as t rc t rc t wc t rc t wc t rc t ah t ceph valid output valid input valid output valid input valid output status bank-to-bank read/write timing diagram notes : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2 enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 we toggle dq 2 and dq 6 with oe or ce dq 2 vs. dq 6 note : dq 2 is read from the erase-suspended sector.
mbm29ds163te/be 10 50 ce ry/by we rising edge of the last write signal t busy entire programming or erase operations ry/by timing diagram during program/erase operations t rp t rb reset t ready ry/by we reset , ry/by timing diagram
mbm29ds163te/be 10 51 t ce t fhqv t elfh a -1 data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) dq 15 ce byte dq 14 to dq 0 dq 15 /a -1 word mode configuration timing diagram t elfl t acc t flqz a -1 data output (dq 14 to dq 0 ) data output (dq 7 to dq 0 ) dq 15 ce byte dq 14 to dq 0 dq 15 /a -1 byte mode configuration timing diagram ce or we byte input valid falling edge of the last write signal t set (t as ) t hold (t ah ) byte timing diagram for write operations
mbm29ds163te/be 10 52 t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 19 , a 18 , a 17 a 16 , a 15 , a 14 a 13 , a 12 a 6 , a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data spax 01h spay sector group protection timing diagram spax : sector group address to be protected spay : sector group address to be protected note : a -1 is v il on byte mode.
mbm29ds163te/be 10 53 unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce reset temporary sector group unprotection timing diagram
mbm29ds163te/be 10 54 v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out spax spax spay t wp t oe 60h 01h 40h 60h 60h data add a 0 a 6 a 1 extended sector group protection timing diagram spax : sector group address to be protected spay : next sector group address to be protected time-out : time-out window = 250 m s (min)
mbm29ds163te/be 10 55 wp/acc v acc v ih we ce ry/by t vlht t vlht v cc t vcs t vaccr t vlht program command sequence acceleration period accelerated program timing diagram
mbm29ds163te/be 10 56 n n n n flow chart 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in progress embedded program tm algorithm embedded algorithm notes : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29ds163te/be 10 57 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence* (address/command) : individual sector/multiple sector* erase command sequence (address/command) : additional sector erase commands are optional. embedded erase tm algorithm embedded algorithm * : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29ds163te/be 10 58 dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation
mbm29ds163te/be 10 59 toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. dq 6 = toggle? dq 5 = 1? read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va start no no yes yes *1 *1, *2 dq 6 = toggle? no yes program/erase operation not complete.write reset command program/erase operation complete read dq 7 to dq 0 addr. = va *1, *2 va = bank addrerss being executed embedded algorithm
mbm29ds163te/be 10 60 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group ? increment plscnt read from sector group addr. = spa, a 0 = v il , a 1 = v ih , a 6 = v il setup sector group addr. a 19 , a 18 , a 17 ,a 16 , a 15 , a 14 , a 13 , a 12 oe = v id , a 9 = v id , a 6 = ce = v il , reset = v ih a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () () * sector group protection algorithm * : a -1 is v il on byte mode.
mbm29ds163te/be 10 61 start perform erase or program operations reset = v id *1 temporary sector group unprotection completed *2 reset = v ih temporary sector group unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again.
mbm29ds163te/be 10 62 start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector group protection completed protection other sector group ? increment plscnt read from sector group address (a 0 = v il , a 1 = v ih , a 6 = v il )* remove v id from reset write reset command time out 250 m s reset = v id wait to 4 m s no yes setup next sector group address device is operating in temporary sector group unprotection mode to sector group protection write sga/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) to verify sector group protection write sga/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) to setup sector group protection write xxxh/60h extended sector group protection entry? extended sector group protection algorithm * : a -1 is v il on byte mode.
mbm29ds163te/be 10 63 555h/aah 555h/20h (ba) xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data? data polling device start no no yes yes set fast mode in fast program reset fast mode embedded programming tm algorithm for fast mode fast mode algorithm
mbm29ds163te/be 10 64 n n n n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of : mbm29ds163 t e 10 tn package type tn = 48-pin thin small outline package (tsop) normal bend tr = 48-pin thin small outline package (tsop) reverse bend pbt = 48-ball fine pitch ball grid array package (fbga) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector device number/description mbm29ds163 16 mega-bit (2 m 8-bit or 1 m 16-bit) cmos flash memory 1.8 v-only read, program, and erase valid combinations valid combinations mbm29ds163te/be 10 tn tr pbt valid combinations list configurations planned to be supported in volume for this device. consult the local fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
mbm29ds163te/be 10 65 n n n n package dimensions C .003 +.001 .007 C 0.08 +0.03 0.17 "a" (stand off height) (.004 .002) 0.10 0.05 0.10(.004) (mounting height) 12.00 0.20(.472 .008) lead no. 48 25 24 1 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48030s-c-6-7 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part * * 0.50(.020) dimensions in mm (inches) C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48029s-c-6-7 c 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * * dimensions in mm (inches) (continued) 48-pin plastic tsop(1) (fpt-48p-m19) 48-pin plastic tsop(1) (fpt-48p-m20) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are +0.15(.006)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are +0.15(.006)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mbm29ds163te/be 10 66 (continued) 48-pin plastic fbga (bga-48p-m11) c 2001 fujitsu limited b48011s-c-5-3 8.00 0.20(.315 .008) 0.38 0.10(.015 .004) (stand off) (mounting height) 6.00 0.20 (.236 .008) 0.10(.004) 0.80(.031)typ (5.60(.220)) (4.00(.157)) 48-?.45 0.10 (48-?018 .004) m ?.08(.003) index h g fed c ba 6 5 4 3 2 1 c0.25(.010) .041 .004 +.006 0.10 +0.15 1.05 dimensions in mm (inches)
mbm29ds163te/be 10 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0303 ? fujitsu limited printed in japan

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